The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the
transistor Q5.
多谢了
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the transistor Q5.
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the transistor Q5.
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the
transistor Q5.
电平调节电路100使输入到第一时钟终端CK1的时钟信号从高电平以预定值降低,并将该信号提供到晶体管Q5的栅极。
试着翻译哈。偶也不是学电的:I[s:8]
在借鉴各位前辈的成果的基础上试译一下:
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the transistor Q5.
——电平调节电路100将送往第一个时钟终端CK1的时钟信号从H电平降低一个预定值,并将此信号送往晶体管Q5的输入端。
(“the gate of ” 不知如何译,但应该就是输入端、控制端的意思)
The level adjustment circuit 100 lowers the clock signal input to the first clock terminal CK1 by a predetermined value from H level and provides the signal to the gate of the
transistor Q5.