CLAIMS
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[Claim(s)]
[Claim 1] The memory array for datastores connected to the data bus, and the judgment circuit which judges whether the data on said data bus are written in said memory array, If the 1st address for writing data in said memory array is held and data are written in said 1st address, said 1st address will be updated. Next, it sets to the memory control approach of FIFO memory equipment of having a light address-pointer circuit holding the 2nd address for writing in data. It judges whether when the 1st data is outputted on said data bus, it is data which said 1st data should write in said memory array in said judgment circuit. The memory control approach of the FIFO memory equipment characterized by cancelling said 1st data when it is judged as a result of a judgment that it is not data which said 1st data should write in said memory array.
[Claim 2] In case it judges whether it is data which said 1st data should write in said memory array Without updating said 1st address currently held in said light address-pointer circuit, in case it carries out in parallel to write-in actuation of said 1st data to said 1st address of said memory array and said 1st data is cancelled The memory control approach of FIFO memory equipment according to claim 1 of performing write-in actuation of said 2nd data to said 1st address of said memory array when the 2nd data is outputted on said data bus.
[Claim 3] The memory control approach of FIFO memory equipment according to claim 1 that said light address-pointer circuit has a rise counter. |
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